The present invention generally pertains to the field of computer networking. More particularly, the present invention is related to the ability of a peripheral component to access and storing data into cache memory of a host computer device.
Computers have become an integral tool used in a wide variety of different applications, such as in finance and commercial transactions, computer-aided design and manufacturing, health-care, telecommunication, education, etc. Computers are finding new applications as a result of advances in hardware technology and rapid development in software technology. Furthermore, a computer system""s functionality is dramatically enhanced by coupling stand-alone computers together to form a computer network. In a computer network, users may readily exchange files, share information stored on a common database, pool resources, and communicate via e-mail and via video teleconferencing.
One popular type of computer network is known as a local area network (LAN). LANs connect multiple computers together such that the users of the computers can access the same information and share data. Typically, in order to be connected to a LAN, a general purpose computer requires an expansion board generally known as a network interface card (NIC). Essentially, the NIC works with the operating system and central processing unit (CPU) of the host computer to control the flow of information over the LAN. Some NICs may also be used to connect a computer to the Internet.
The NIC, like other peripheral component devices, requires a device driver which controls the physical functions of the NIC and coordinates data transfers between the NIC and the host operating system. An industry standard for interfacing between the device driver and the host operating system is known as the Network Device Interface Specification, or NDIS, which is developed by Microsoft(copyright) Corporation of Redmond, Wash. The operating system layer implementing the NDIS interface is generally known as an NDIS wrapper. Functionally, the NDIS wrapper arbitrates the control of the device driver between various application programs and provides temporary storage for the data packets.
In the networking industry, a standard has been developed for allowing a networked personal computer (PC) which is in sleep mode to be awakened. More specifically, Advanced Micro Devices(copyright) (AMD) of Santa Clara, Calif. has developed a technology referred to as the MAGIC PACKET(copyright) technology. In the Magic Packet technology, assuming, for example, that an Ethernet controller is running and communicating with the network, the PC""s power management hardware or software puts the Ethernet controller into the MAGIC PACKET(copyright) mode prior to the system going to sleep. Once in the sleep, the PC will be awakened when a MAGIC PACKET(copyright) is detected. That is, incoming data will be monitored until the specific sequence comprising the MAGIC PACKET(copyright) is detected. A MAGIC PACKET(copyright) consists of 16 duplications of the IEEE (Institute of Electrical and Electronics Engineers) address of the destination node, with no breaks or interruptions. The MAGIC PACKET(copyright) can be located anywhere within incoming packets, but must be preceded by a synchronization stream. The synchronization stream allows the scanning state machine to be much simpler. The synchronization stream is defined as at least 6 bytes of FFh (i.e. a byte of all 1""s; and wherein h stands for hexadecimal). The device will also accept a multicast frame, as long as the 16 duplications of the IEEE address match the address of the machine to be awakened.
As an example, if the IEEE address for a particular node on the network was 11h 22h 33h 44h 55h 66h, then the LAN controller would be scanning for the data sequence (assuming an Ethernet Frame):
Unfortunately, detection of a MAGIC PACKET(copyright) is complicated in a 16-bit wide bus environment. Specifically, in such an environment, there is no way to determine whether the MAGIC PACKET(copyright) data pattern will start aligned on a 16-bit boundary or on an 8-bit boundary. That is, in order to accurately and efficiently utilize MAGIC PACKET(copyright) technology in a 16-bit bus environment, it is necessary to know whether the streaming data packet (i.e. the MAGIC PACKET(copyright)) has a first alignment (e.g. the MAGIC PACKET(copyright) has an even-alignment), or whether the streaming data packet has a second alignment (e.g. the MAGIC PACKET(copyright) has an odd-alignment).
One approach to solve the above described problem is to employ two processing units. The first processing unit would be configured to handle a streaming data packet having the aforementioned first alignment. Conversely, the second processing unit would be configured to handle a streaming data packet having the aforementioned second alignment. Such a coarse solution is not practical, however. Using two processing units is wasteful and increases system cost. Furthermore, such an approach is typically unable to detect when the MAGIC PACKET(copyright) starts with more than 6 FFh.
Thus, a need exists for a system and method which efficiently handles a particular streaming data packet regardless of whether the streaming data packet has a first alignment or a second alignment. A further need exists for a system and method meets the above-listed need and wherein the method and system is able to handle the streaming data packet using only a single processing unit regardless of whether the streaming data packet has a first alignment or a second alignment.
The present invention provides a system and method which efficiently handles a particular streaming data packet regardless of whether the streaming data packet has a first alignment or a second alignment. The present invention further provides a system and method achieves the above-listed accomplishment and wherein the method and system is able to handle the streaming data packet using only a single processing unit regardless of whether the streaming data packet has a first alignment or a second alignment.
Specifically, in one embodiment of the present invention, the present invention receives a first portion of an incoming packet stream at a peripheral component adapted to be coupled to a host computer. The present embodiment then receives a second portion of the incoming packet stream at the peripheral component. Next, the present embodiment determines whether the incoming packet stream has a first alignment or a second alignment. Provided that the incoming packet stream has the second alignment, the present embodiment reconfigures the incoming packet stream to have the first alignment. The present embodiment then handles the incoming packet stream using a single processing unit adapted to handle only packet streams having the first alignment. In so doing, the present invention is able to handle an incoming packet stream having either a first alignment or a second alignment without requiring multiple processing units.
In another embodiment, the present invention includes the features of the above-described embodiment and includes additional recitation. Specifically, the present embodiment recites that the first portion of the incoming packet stream is a first 16 bit word thereof, and that the second portion of the incoming packet stream is a second 16 bit word thereof. In this embodiment, the present invention determines whether the incoming packet stream has a first alignment or a second alignment by combining a first byte of the second 16 bit word with a second byte of the first 16 bit word to form a new 16 bit word. In the new 16 bit word, the first byte of the new 16 bit word is the second byte of the first 16 bit word. Additionally, the second byte of the new 16 bit word is the first byte of the second 16 bit word. Next, provided the new 16 bit word is FFFFh, the present embodiment assumes that the incoming packet stream has an odd-alignment. However, provided that the new 16 bit word is not FFFFh, and provided that the second 16 bit word is FFFFh, the present embodiment assumes that the packet stream has an even-alignment.